NXP Semiconductors /MIMXRT1011 /FLEXRAM /INT_STAT_EN

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Interpret as INT_STAT_EN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ITCM_MAM_STAT_EN_0)ITCM_MAM_STAT_EN 0 (DTCM_MAM_STAT_EN_0)DTCM_MAM_STAT_EN 0 (OCRAM_MAM_STAT_EN_0)OCRAM_MAM_STAT_EN 0 (ITCM_ERR_STAT_EN_0)ITCM_ERR_STAT_EN 0 (DTCM_ERR_STAT_EN_0)DTCM_ERR_STAT_EN 0 (OCRAM_ERR_STAT_EN_0)OCRAM_ERR_STAT_EN

OCRAM_ERR_STAT_EN=OCRAM_ERR_STAT_EN_0, DTCM_ERR_STAT_EN=DTCM_ERR_STAT_EN_0, DTCM_MAM_STAT_EN=DTCM_MAM_STAT_EN_0, ITCM_MAM_STAT_EN=ITCM_MAM_STAT_EN_0, ITCM_ERR_STAT_EN=ITCM_ERR_STAT_EN_0, OCRAM_MAM_STAT_EN=OCRAM_MAM_STAT_EN_0

Description

Interrupt Status Enable Register

Fields

ITCM_MAM_STAT_EN

ITCM Magic Address Match Status Enable

0 (ITCM_MAM_STAT_EN_0): Masked

1 (ITCM_MAM_STAT_EN_1): Enabled

DTCM_MAM_STAT_EN

DTCM Magic Address Match Status Enable

0 (DTCM_MAM_STAT_EN_0): Masked

1 (DTCM_MAM_STAT_EN_1): Enabled

OCRAM_MAM_STAT_EN

OCRAM Magic Address Match Status Enable

0 (OCRAM_MAM_STAT_EN_0): Masked

1 (OCRAM_MAM_STAT_EN_1): Enabled

ITCM_ERR_STAT_EN

ITCM Access Error Status Enable

0 (ITCM_ERR_STAT_EN_0): Masked

1 (ITCM_ERR_STAT_EN_1): Enabled

DTCM_ERR_STAT_EN

DTCM Access Error Status Enable

0 (DTCM_ERR_STAT_EN_0): Masked

1 (DTCM_ERR_STAT_EN_1): Enabled

OCRAM_ERR_STAT_EN

OCRAM Access Error Status Enable

0 (OCRAM_ERR_STAT_EN_0): Masked

1 (OCRAM_ERR_STAT_EN_1): Enabled

Links

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